Showing posts with label JFET Experiments. Show all posts
Showing posts with label JFET Experiments. Show all posts

15 April 2014

JFET measurements continued

Since I am now getting ready to build the second oscillator for the RF signal source (10MHz - 45MHz) I thought it would be instructive to test a few more MPF102's for this oscillator. The same test fixture was used as previous (see Label JFET Experiments). Results as follows:

Vd-d = 10.04V

SAMPLE     Idss (mA)    Vp (Volts)
1B                  9.8              -2.75
2B                  7.3              -2.83    
3B                  9.98            -3.51
4B                  9.2              -2.4

Sample 4B was a re-measure of the previous Sample 1 and yielding similar results. Tests were carried out quicker this time to minimize the effects of sample heating with the smaller resistance range.

Sample 3B has the widest dynamic range between Vp and Idss. Start with that sample in the oscillator and then measure the output when compared to sample 4B which is the most linear.

Sample 1B
Sample 2B
Sample 3B

Sample 4B








02 April 2014

RF signal source. Oscillator prototype build & test

I am in the process of building an RF Signal Source as per EMRFD Fig 2.27. This is a Hartley design and incorporates 2 oscillators. The first covering a nominal 2-10MHz and the second covering a nominal 10-45MHz.

The Hartley topology is chosen for two reasons. a) The capacitor in the resonator can be fully variable and thus allows a wide range of frequency coverage unlike the Colpitts where, by definition, the feedback capacitors are fixed. b) The oscillator exhibits a reasonably flat output power over a wide frequency range.

Having built the chassis, installed the variable capacitors and cut the panels for the enclosure, I was now in a position to build a rough prototype of one of the oscillators. I chose the lower frequency oscillator. This took me a few hours to build. Since I don't have any of the specified 2N4416 JFETS, I decided to start with an MPF102. I selected sample 2 (Ref JFET experiments blog)  since it had a lower pinch-off voltage and higher Idss than sample 1, although not as good in performance as the tested J310. I decided to start with just the 400pf variable capacitor. This should allow easier troubleshooting since there are fewer parts. (refer to the schematic attached).

The oscillator powered up first time with no issues. The oscillator turn on voltage Vdd was 1.96V. Maximum output was obtained with a Vdd of 7.58V. Thus there was an excess of current flowing in the drain as Vdd was increased to 12V. The scope output waveform 'looks' clean. I have no way of measuring the harmonic distortion. Could increasing the rail voltage beyond 7.58V result in an increase of harmonic distortion?

The 3 turn link output was first terminated in a 50 ohm feed thru connector which was connected to the scope channel 1. This channel is also fed to the frequency counter. Then the output was connected to the Power Meter.

The oscillator is reasonably stable and certainly acceptable for general measurements and can be improved upon with more careful construction. Measuring at a frequency of 7030.44kHz and starting at 08:30 am the oscillator drifted upwards to 7030.46KHz after 23 minutes (10Hz). The shack door was closed. No thermometer is available. Then with the shack door opened and after another 10 minutes the oscillator was at 7030.73KHz. It then started to rain which presumably lowered the temperature the frequency measured was 7031.02KHz (562Hz). On blowing on the parts with a straw the indications were that the 10pf capacitor was the biggest drift contributor. As the temperature decreases the oscillator frequency increases.  Neither the JFET or the inductor seemed to be significant contributors. No vibration tests were carried out, however it was easy to tune the large capacitor to within 1KHz of the desired frequency. More precise tests needed once the buffer is built.

An error was discovered in the design. The Large 400pF variable capacitor wire runs parallel to the 30pf bandspread capacitor for about 4 inches. Although this capacitor was not connected it changed the oscillator frequency when it's capacitance was varied. Action here is to re-route the large capacitor wire in a different direction.

Tests with the Power meter showed an output variation of just over 1dB from an Fmin output of -1.33dBm at 2810KHz to -0.27dBm (frequency not measured but around 6000KHz). The output power at Fmax of 13663KHz = -0.75dBm. These measurements are in line with  those stated in EMRFD and very satisfactory.

Scope measurements
Fmax = 13663KHz (this frequency will decrease as the bandspread capacitors are added)
Fmin = 2810KHz (This frequency will increase as the bandspread capacitors are added)
Fmin Vpk-pk = 6div*0.1 = 0.6V (~0.5dBm)
Fmax Vp-p = 5.5div*0.1 = 0.55V
F(7175KHz) = 0.6V
Power Meter measurements
Fmin = DVM = 1770mV, thus Power = -86.29+(0.048*1770) = -1.33dBm
Fmax = DVM = 1782mV thus Power = -86.29+(0.048*1782) = -0.75dBm
Fpk = DVM = 1792mV thus Power = -86.29+(0.048*1792) = -0.27dBm

Next steps
Reroute the capacitor wiring.
Try different 10pf capacitors to try to improve thermal stability
Try a J310 JFET.



Prototype Hartley oscillator 2.8MHz - 13.7MHz

Pic showing the large variable and bandspread variable and oscillator circuit with terminations.

Oscillator set at 7030.64KHz with scope waveform showing no 'visible distortion'. Harmonic level not measured. The feedthrough 50 Ohm terminator on channel 1 can be seen. 





09 March 2014

JFET biasing experiments

Today I continued with the biasing experiments. I redid the tests for Sample 1 and MPF102 and the results were the same as previous measurements.

I then ran the same tests on Sample 2 MPF102 and Sample 3 J310

The results are shown below for sample 2 and 3.

Using the FET equation to try to achieve a curve fit I estimate the Vp and Idss values as follows:

Vdd = 10.18V

SAMPLE        Vp        Idss
1 MPF102      -2.27      9mA
2 MPF102      -3.6        9.7mA
3 J310             -2.98     33.8mA

For the J310 the specification states that Idss can fall between 12mA and 30mA. Clearly this sample is at the upper end.

According to this analysis sample 1 would have the lowest power output and the J310 the highest. Next step will be to build a Hartley oscillator and measure the power outputs.

JFET test fixture

Sample 2 MPF102
Sample 2 MPF102
Sample 3 J310
Sample 3 J310