09 March 2014

JFET biasing experiments

Today I continued with the biasing experiments. I redid the tests for Sample 1 and MPF102 and the results were the same as previous measurements.

I then ran the same tests on Sample 2 MPF102 and Sample 3 J310

The results are shown below for sample 2 and 3.

Using the FET equation to try to achieve a curve fit I estimate the Vp and Idss values as follows:

Vdd = 10.18V

SAMPLE        Vp        Idss
1 MPF102      -2.27      9mA
2 MPF102      -3.6        9.7mA
3 J310             -2.98     33.8mA

For the J310 the specification states that Idss can fall between 12mA and 30mA. Clearly this sample is at the upper end.

According to this analysis sample 1 would have the lowest power output and the J310 the highest. Next step will be to build a Hartley oscillator and measure the power outputs.

JFET test fixture

Sample 2 MPF102
Sample 2 MPF102
Sample 3 J310
Sample 3 J310

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